In order to secure a breakdown voltage of a semiconductor device, a breakdown voltage holding structure such as a field limiting ring (FLR) layer is formed in a non-cell region on a circumference side of the semiconductor substrate. Further, in order to secure reliability of the semiconductor device, a field plate is formed on a front side of the FLR layer. In a semiconductor device described in Japan Patent Application Publication No. 2009-38356 (JP 2009-38356 A) (Patent Document 1), a field plate including a plurality of metal layers and a plurality of polysilicon layers is formed on a front side a plurality of FLR layers. The plurality of FLR layers is provided so as to surround a cell region, and to be disposed at intervals in a direction perpendicular to a longitudinal direction thereof. The metal layers and the polysilicon layers are formed so as to correspond to the plurality of FLR layers, and are disposed along their corresponding FLR layers. The polysilicon layer is formed in an insulating film formed on a front surface of a semiconductor substrate. The metal layer is formed on a front surface of the insulating film, and partially penetrates through the insulating film so as to reach the FLR layer. Further, the polysilicon layer and the metal layer make contact with each other, so as to be electrically connected with each other.